1. Technical Field of the Invention
This invention is related to methods, devices and systems for enhancing reset and built-in self-test mechanisms for input/output (I/O) device adapters. Specifically, the invention includes enhanced I/O device resets that bring the I/O device adapter and the I/O device connected thereto into one of several defined reset states thereby permitting a greater degree of control over I/O devices, adapters, and their components and bringing these elements into a well-defined, predictable state. This invention has particular application to I/O device adapters and systems conforming to the PCI (peripheral component interconnect) local bus specification.
2. Description of Related Art
The PCI local bus is an industry standard I/O bus that interconnects computer processor complexes to I/O device adapters. The computer processor complex typically contains a central processing unit (CPU) and system main storage facilities. A PCI I/O device adapter contains hardware, and possibly additional processors, memory and programming to interconnect I/O devices such as disks, computer network interfaces, and so forth, to the processor complex and to control the functions of these I/O devices.
The PCI local bus specification was developed and is controlled by a special interest group of I/O device and computer system vendors influential in the personal computer and PC server industry. This specification is defined expressly as a higher performance replacement for the existing standard I/O bus architectures such as the IBM microchannel and extended industry standard architecture. As such, the PCI local bus specification is the dominant I/O bus architecture within a very large segment of the computer industry. Furthermore, the PCI local bus specification has been embraced outside of this segment by vendors that participate primarily in other markets, such as enterprise-class network server and mainframe computers. Thus, the scope of computer system and I/O device products that employ PCI local bus implementations is rapidly becoming the majority within the overall computer industry.
FIGS. 1 and 2 illustrate the basic elements of a conventional PCI local bus implementation including a processor complex 100 having a central processing unit (CPU) 110 and memory 120 interconnected by a processor memory bus 130. The conventional PCI local bus implementation further includes a PCI backplane 200 that is typically a motherboard with a PCI local bus 230, and PCI connectors 205, 206 that interconnect PCI I/O device adapters to the PCI local bus 230.
PCI connectors 205, 206 are mounted to slots on the PCI local bus 230 and may either be a removable-type connector 205 or an embedded, nonremovable connector 206. The PCI connector 205 interconnects the PCI local bus 230 and PCI device 240. The implementation shown in FIGS. 1 and 2 illustrates a removable PCI device 240 that may be easily disconnected from the local bus 230 via a PCI connector 205. The PCI connectors 205 also interconnect the PCI local bus 230 and a PCI multifunction device 260 as shown in FIG. 2.
FIG. 1 is particularly directed to a system of single function devices connected to a PCI local bus including a removable PCI device 240 having a single function I/O adapter 250 connected therein and two I/O device adapters 252, 254 connected directly to a slot in the PCI local bus 230. PCI device 240 includes an I/O device adapter 250 that behaves as a singular unit on the PCI local bus 230 with respect to its interconnections to PCI local bus 230 and participation in PCI bus signaling protocols. Thus, PCI device 240 and the I/O device adapter 250 are typically referred to as a "single function" PCI device.
FIG. 2 is particularly directed to a system of PCI single function and multifunction devices. The PCI single function device includes a removable PCI device 240 having a single function PCI I/O adapter 250 connected therein. The PCI multifunction device 260 includes a plurality of I/O device adapters 252,254, hence the term "multifunction" device.
Although the same I/O device adapter 250 may be utilized within the PCI multifunction device 260 as the single function device 240, reference numerals 252 and 254 are utilized for the I/O device adapters within the multifunction device 260 to indicate optional structure and functionality such as the addition of a processor and memory to implement an I/O processor, or to indicate that the I/O device adapter 252,254 may be unique with respect to the type of I/O device attached thereto.
A function router 270 is included within the PCI multifunction device 260 to interconnect the I/O device adapters 252,254 to the PCI local bus 230. Typically, the function router 270 may be implemented with a multiplexer such that data and/or control signals may be routed between the processor complex 100 and the selected I/O device adapter 252 or 254. The processor complex 100 may individually address the single function PCI device 240 or the PCI multifunction device 260 using a unique device identifier assigned to each PCI local bus connection in which a PCI device 240, 260 can be attached. In other words, a unique device identifier is assigned to each slot in which the PCI connector 205 is inserted. This device identifier is the IDSEL, defined by the PCI local bus specification, utilized to uniquely select a desired I/O device on the PCI local bus 230 during PCI configuration read or configuration write signaling protocols.
The configuration protocol defined within the PCI local bus specification allows the processor complex 100 to individually address each PCI local bus device 250, 260 using a physical selection signal that is part of the PCI bus signal definitions. The specification further assigns to each I/O device adapter 250, 252, 254 a range of processor memory addresses by which the CPU 110 may subsequently communicate with the I/O device adapters 250, 252, 254.
The PCI multifunction device 260 serves to collect multiple PCI I/O device adapters 252,254 using a single PCI local bus connection. This arrangement is quite practical in that it allows for the evolution from larger physical components to more dense physical integration as components become smaller. Furthermore, this arrangement exploits dense packaging of multiple I/O device adapters 252, 254 to connect an overall increased number of I/O device adapters 252, 254 without adding more connections on the PCI local bus 230 or its backplane 200.
The function router 270 in the PCI multifunction device 260 effectively replaces the two required PCI bus connections with a single PCI bus connection 205. To enable the processor complex 100 to select a particular I/O device adapter 252 or 254 within this multifunction device, the PCI local bus specification configuration protocol appends a function number that ranges in value from 0 to 7 to the device identifier. The PCI local bus specification interchangeably uses the word "function" to refer to the I/O device adapters 250, 252, 254. Single function devices such as PCI device 240 are accommodated in this extended definition by implicitly responding as function zero within the scope of the device ID that selects its PCI bus connection. In essence, the single function PCI device 240 is accommodated within the expanded definition of multifunction device protocols and may be implemented therein by utilizing the function router 270 which merely implements only one function (function zero).
Given that the function number ranges in value from 0 to 7, a PCI multifunction device 260 is then architecturally capable of incorporating up to eight I/O device adapter elements within a single device that requires a single slot on the PCI local bus 230. The role of the function router 270 is to facilitate the sharing of the single slot amongst the multiple I/O device adapters 252,254 incorporated within the multifunction device 260. In particular, during configuration read and write protocols, the function router 270 uses the function number from this protocol to route the arguments of this protocol between the PCI local bus 230 and the associated PCI I/O device adapters 252 or 254 within the multifunction device 260.
The PCI local bus specification provides for a PCI device reset that is activated by sending a reset signal (RST#) to a designated pin on a PCI compliant device. The reset signal (RST#) is activated during power up or power down of the PCI device, during error recovery procedures, or upon a power failure. More specifically, the reset signal (RST#) asynchronously disables (floats) the outputs of PCI components and generally resets the PCI bus interface elements of the I/O device adapter, wherein the states of some elements are defined and some are not.
One limitation of the PCI local bus specification is the lack of a well-defined reset procedure or a reset state that permits the I/O device adapter to exhibit predictable behavior during and after the reset. In other words, the PCI local bus specification contains incomplete and ill-defined procedures and mechanisms for performing a reset. This incomplete definition leads to different and perhaps unpredictable effects for each vendor-specific implementation of a PCI compatible device.
Another limitation of the PCI local bus specification is the lack of a variety of resets. The PCI reset signal (RST#) only specifies a reset state that is directed at a limited set of PCI bus interface elements but that does not address the states of other elements of the I/O device adapter or I/O devices connected thereto.
Yet another limitation of the PCI local bus specification is the lack of a directed reset that affects a selected I/O device or single functions within a multifunction device without affecting other, non-selected I/O devices or single functions of a multifunction device connected to the PCI local bus. Thus, the PCI local bus specification does not specify a granular control of components within a single function device or for a specific function within a multifunction device. Currently, only the reset signal (RST#) is specified which implicitly affects all entities connected to the PCI local bus including the entirety of a single-function device and all functions within a multifunction device.
Still another limitation of the PCI local bus specification is the rudimentary built-in self-test facility outlined in the PCI local bus specification. The PCI local bus specification merely defines a built-in self test register consisting of a built-in self-test capable bit indicating whether the device is capable of performing a built-in self-test, a stall built-in self-test field that triggers the initiation of a built-in self-test, and a completion code field that stores a completion code upon completion of the built-in self-test. The PCI specification lacks a built-in self-test mechanism having control sequences, synchronization, and completion signals particularly for (1) a multifunction device as a whole and (2) individual PCI device functions within a multifunction device.